Various infrared devices, including but not limited to device imagers formed on a semiconductive substrate, are described in Wolfe, et al., The Infrared Handbook, Office of Naval Research, Department of Navy, 1978, particularly at pages 12-27 through 12-54. Such imagers typically comprise a photodetector, some type of storage component which integrates the detector's photocurrent, and a multiplexing circuit. In the case of charge coupled imagers, the multiplexing circuit is generally implemented with a CCD by an array of parallel charge coupled device serial registers which receive the integrated charge from adjacent photodetectors on the substrate. Often the parallel CCD registers are arranged in vertical columns, all of their outputs being connected to a single horizontal CCD register which serves as a multiplexer for the output signals. The column CCD registers are connected to a common input diffusion and common input gate which separately introduces a bias charge, termed a FAT zero charge packet, into each of the registers.
The imaging ability of such devices is basically noise limited. It is necessary to deal with at least the following noise sources: (1) bias level noise on the reset level, (2) bias level noise on the substrate level, (3) kTC or switching noise, and (4) 1/f noise associated with source followers.
Certain techniques for reducing the effect of such noise sources on the signals produced by CCD imagers are described in a patent application titled "Low Noise Charge Coupled Imager Circuit" by M. J. Hewitt and A. L. Morse, filed with the United States Patent and Trademark Office on Jan. 17, 1983 as Ser. No. 458,607 and assigned to Hughes Aircraft Company. The present invention concerns a technique, and circuits based thereon, for further and significantly minimizing the effects of noise on the output of CCD imagers or any type of integrating infrared device, including a few simple elements on the semiconductor substrate at the output of the multiplexing circuitry or adjacent to each photodetector. As a result of such noise reduction circuits and technique, it is feasible to employ surface channel enhancement mode devices instead of buried channel devices, which do not perform well in the low temperatures typical of many space sensor systems. However, surface channel circuits are susceptible to 1/f noise; the circuits and technique disclosed herein minimize such 1/f noise. Because of the reduction of noise in the output signal achieved for each IR detector using the techniques and circuits described herein, the resulting imagers can be used effectively in high EMI environments. Also, the noise limitations imposed on drive electronics for the imagers can be reduced.
In addition to the low noise features of the circuits and technique disclosed herein, they have the additional advantage of not requiring a full-frame memory to establish differences in signal levels, and in turn the output signal for each photodetector. This reduces the number of digitizations required to process the resulting data, and also reduces the number of bits used in the A/D conversion process. Also, since all capacitors in the circuitry of the arrays disclosed herein can be set at once rather than individually, the number of transitions of the output occurring while a pixel is addressed is reduced. This permits faster readout rates to be employed, and causes less power dissipation since the output can slew at a slower rate. Moreover, the new technique and circuits described herein can be used in a radiation environment since they reduce the effects of (1) threshold drift, (2) increased 1/f noise of the source follower, and (3) increased surface mobility.